1. Field of the Invention
The present invention relates to unaligned access to memory. In one example, the present invention relates to methods and apparatus for allowing unaligned access to memory using an adapter on a programmable device.
2. Description of Related Art
Systems that use memory typically have addresses associated with various memory lines. In some instances, each memory line is one byte in length. Every byte in memory is provided with a unique address. In these systems, master components such as processors, Direct Memory Access (DMA) controllers, Ethernet controllers, etc., access memory using byte aligned addresses. Each memory read or write operation has an associated address. The address indicates which byte or corresponding memory line is being accessed.
To increase performance, multiple bytes of memory are often accessed simultaneously. For example, a 32-bit processor accesses 4 bytes at a time. A 64-bit processor would access 8 bytes at a time. This remains true even if there actually are only a few bits of useful information included in the 8 bytes. Nonetheless, the master component reads the few bits of useful information by providing the address of the first byte of the 8 byte memory block. For any wide-access, the multiple target bytes in memory are located at contiguous addresses.
Similarly, a 32-bit-wide memory produces four bytes on its data-port for any read-operation even if the accessing master component is only interested in the byte at address 0. The bytes at addresses 1, 2, and 3 will be read from the memory anyway. Wide memories are universally built such that all read and write accesses must be aligned. An aligned access is one where the byte-address is evenly-divisible by the width of the memory (in bytes). Thus, an aligned-access to a 32-bit-wide memory would be any access to an address divisible by four. Read and write operations to a 32-bit-wide (4-byte-wide) memory are made to addresses 0, 4, 8, 12, 16, etc. Read and write operations to 64-bit (8-byte-wide) memory are made to addresses 0, 8, 16, 24, 32, and so on.
In some systems, issuing an unaligned read or write operation to a wide memory will produce an undefined result. In most systems, an unaligned read or write operation will behave as if the address were truncated downward or rounded downward to the next-lower aligned address.
However, conventional mechanisms for allowing unaligned access to memory are limited, particularly for programmable devices. Consequently, the techniques of the present invention provide additional efficient mechanisms for allowing unaligned memory access.